This application is based upon and claims priority of Japanese Patent Application No. 2002-255136, filed on Aug. 30, 2002, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a capacitor and a method of manufacturing the same.
2. Description of the Prior Art
The nonvolatile memory element having the ferroelectric capacitor, which is called FeRAM or FRAM, is put on the market as the semiconductor memory. This nonvolatile memory element has features of a high-speed operation; low power consumption, and the large number of writing times, and its future development is anticipated.
As the capacitor formed in the memory cell area of such nonvolatile memory element, the planar type and the stacked type are known.
The planar capacitor has such a structure that the first wiring formed on the insulating layer, which covers the capacitor, is connected to the upper electrode via the first contact hole and the second wiring formed on the insulating film is connected to the lower electrode via the second contact hole.
The stacked capacitor has such a structure that the lower electrode is directly formed on the conductive plug formed in the insulating layer as the underlying layer of the capacitor. However, since the ferroelectric material and the lower electrode material constituting the capacitor are grown to take over the orientation of the underlying layer, the underlying layer must be made flat and formed of single material. Also, since the oxygen is indispensable to form the ferroelectric material and the lower electrode material is ready to transmit the oxygen, the conductive plug is oxidized to cause the defective contact readily.
Therefore, currently the planar capacitor is employed in most of FeRAMs that are available on the market.
The memory cell having the planar capacitor has a structure showing in FIG. 1 to FIG. 3, for example. FIG. 1 is a plan view showing a part of the memory cell area of FeRAM, and insulating layers except the element isolation insulating layer are omitted from the illustration.
FIG. 2 is a sectional view taken along a Ixe2x80x94I line in FIG. 1, and FIG. 3 is a sectional view taken along a IIxe2x80x94II line in FIG. 1.
In FIG. 1, a well region 103 that is surrounded by an element isolation insulating layer 102 is formed on a silicon substrate 101. Then, MOS transistors 107a, 107b having a sectional structure shown in FIG. 2 are formed in the well region 103. Then, a planar capacitor 100 having a sectional structure shown in FIG. 2 and FIG. 3 is formed on the side of the well region 103.
In FIG. 2, two gate electrodes 105a, 105b are formed over the well region 103, which is surrounded by the element isolation insulating layer 102, of the silicon substrate 101 via a gate insulating layer 104. Also, impurity diffusion regions 106a, 106b. 106c having the LDD structure are formed in the silicon substrate 101 on both sides of the gate electrodes 105a, 105b. The first MOS transistor 107a consists of one gate, electrode 105a, the impurity diffusion regions 106a, 106b, etc. Also, the second MOS transistor 107b consists of the other gate electrode 105b, the impurity diffusion regions 106b, 106c, etc.
The element isolation insulating layer 102 and the MOS transistors 107a, 107b are covered with first and second insulating layers 108, 109. An upper surface of the second insulating layer 109 is planarized by the CMP (Chemical Mechanical Polishing) method, and the ferroelectric capacitor 100 is formed on the upper surface.
The ferroelectric capacitor 100 has a lower electrode 100a having a contact area, a ferroelectric layer 100b, and an upper electrode 100c. Then, a third insulating film 110 is formed on the capacitor 100 and the second insulating layer 109. The lower electrode 100a is formed by patterning a platinum layer. Also, the ferroelectric layer 100b is formed by patterning a PZT layer, for example. Then, the upper electrode 100c is formed by patterning an iridium oxide layer, for example.
In the first to third insulating layers 108 to 110, a first contact hole 110b is formed on the impurity diffusion region 106 between two gate electrodes 104a, 104b and also second and third contact holes 110a, 100c are formed on the impurity diffusion regions 106a, 106c located near both ends of the well region 103 respectively. Also, as shown in FIG. 3, a fourth contact hole 110d is formed on the contact area of the lower electrode 100a. 
First to fourth conductive plugs 111a to 111d made of an adhesive layer and a tungsten layer respectively are formed in the first to fourth contact holes 110a to 110d. Also, a fifth contact hole 112 is formed on the upper electrode 100c of the capacitor 100.
A first wiring 120a, which is connected to an upper surface of the first conductive plug 111a and is connected to the upper electrode 100c via the fifth contact hole 112, is formed on the third insulating layer 110. Also, a second wiring 120c, which is connected to an upper surface of the third conductive plug 111c and is connected to another upper electrode 100c via another fifth contact hole 112, is formed on the third insulating layer 110. Also, a conductive pad 120b is formed on the second conductive plug 111b and the neighboring third insulating layer 110.
In addition, as shown in FIG. 3, a third wiring 120d, which is connected to an upper surface of the contact area of the lower electrode 100a via the fourth conductive plug 111d, is formed on the third insulating layer 110.
A fourth insulating layer 121 is formed on the first, second, and third wirings 120a, 120c, 120d, the conductive pad 120b, and the third insulating layer 110. A sixth contact hole 121a is formed in the fourth insulating layer 121 on the conductive pad 120b. A bit-line conductive plug 122 is formed in the sixth contact hole 121a. Also, a bit line 123 that is connected to the bit-line conductive plug 122 is formed on the fourth insulating layer 121.
By the way, in the above planar capacitor 100, as shown in FIG. 3, the contact area of the lower electrode 100a of the capacitor 100 is exposed from the ferroelectric layer 100b before the third insulating layer 110 is formed.
If the reducing gas is employed as the reaction gas when the fourth conductive plug 111d is to be formed on the lower electrode 100a, such reaction gas is supplied to the lower electrode 100a of the capacitor 100 via the contact hole 110d and then is moved along the lower electrode 100a to reduce the ferroelectric layer 100b. Therefore, the deterioration of the characteristics of the capacitor 100 that is formed in the area that is located in vicinity of the fourth conductive plug 111d is caused. Also, since the lower electrode 100a made of platinum is exposed from the ferroelectric layer 100b in the contact area to the fourth conductive plug 111d, the characteristics of the capacitor 100 located near the contact area are ready to deteriorate because of the catalytic action of the platinum.
It is an object of the present invention to provide a semiconductor device capable of suppressing deterioration of a capacitor in an area located in vicinity of a contact portion between a lower electrode and a wiring, and a method of manufacturing the same.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a first insulating layer formed on a semiconductor substrate; a conductive pattern formed on the first insulating layer; a second insulating layer for covering the conductive pattern; a first hole formed in the second insulating layer on the conductive pattern; a lower electrode of a capacitor formed on the second insulating layer and having a contact area, a lower surface of which is connected electrically to the conductive pattern via the first hole; a dielectric layer of the capacitor formed on the lower electrode; an upper electrode of the capacitor formed on the dielectric layer in regions except the contact area; a third insulating layer formed on the upper electrode and the second insulating layer; a second hole formed in the third insulating layer and the second insulating layer on the conductive pattern at an interval from the first hole; and a lower electrode leading wiring formed on the third insulating layer to be connected electrically to the conductive pattern via the second hole.
According to another aspect of the present invention, there, is provided a manufacturing method of a semiconductor device comprising the steps of: forming a first insulating layer on a semiconductor substrate; forming a conductive layer on the first insulating layer; forming a conductive pattern by patterning the conductive layer; forming a second insulating layer on the conductive pattern and the first insulating layer; forming a first hole in the second insulating layer on the conductive pattern; forming a lower electrode conductive layer in the first hole and on the second insulating layer; forming a dielectric layer on the lower electrode conductive layer; forming an upper electrode conductive layer on the dielectric layer; forming a capacitor upper electrode in a region that is away from the first hole by patterning the upper electrode conductive layer; forming a capacitor dielectric layer under at least the upper electrode by patterning the dielectric layer; forming a capacitor lower electrode, which is connected electrically to the conductive pattern, in areas containing a range that extends from a lower surface of the capacitor dielectric layer to an inside of the first hole by patterning the lower electrode conductive layer; forming a third insulating layer on the capacitor lower electrode, the capacitor dielectric layer, and the capacitor upper electrode, and the second insulating layer; forming a second hole in the third insulating layer and the second insulating layer on the conductive pattern at an interval from the first hole; and forming a lower electrode leading wiring, which is connected electrically to the conductive pattern via the second hole, on the third insulating layer.
According to the present invention, the first insulating layer, the conductive pattern, the second insulating layer, the capacitors, the third insulating layer, and the lower electrode leading wiring are formed sequentially over the semiconductor substrate, then the lower electrode of the capacitor is connected to the upper surface of the conductive pattern, and then the lower electrode leading wiring is also connected electrically to the conductive pattern from its upper side.
Therefore, in order to extend electrically the lower electrode onto the third insulating layer, there is no need that the lower electrode leading wiring should be connected to the upper surface of the lower electrode. Hence, the step of forming the contact hole on the lower electrode is omitted, and thus the lower electrode is never exposed to the reducing gas via the contact hole. As a result, the reducing gas is prevented from being supplied to the ferroelectric layer along the lower electrode, and thus the degradation of the capacitor is prevented.
In addition, the overall upper surface of the lower electrode can be covered with the dielectric layer.
Therefore, the deterioration of the ferroelectric layer caused due to the catalytic action of platinum constituting the lower electrode can be suppressed in the steps executed after the capacitor is formed, and thus the characteristics of the capacitor can be maintained satisfactorily.